Generally, an IC device may include various components and elements such as memory cells, processor cores, analog circuits, or the like. Additionally, an IC device may include contacts and vias for interconnecting the components, which may be in close proximity at a same or different layer in the IC device. For example, a transistor may include a gate contact that may be connected by a via to a metal layer above the gate contact. There are different processes and methods that are utilized by the semiconductor industry to manufacture/fabricate an IC device. With advances in these methods/processes and industry demands for more efficient and smaller sized IC devices, physical dimensions of the components and elements integrated into the IC devices are continuously reduced. Also, spaces separating the components/elements/contacts from each other are also reduced, which can give rise to various challenges in the manufacturing of such IC devices. For example, photolithography processes may be utilized to pattern various shapes onto a surface of a silicon (Si) substrate for creating the components in an IC device. However, smaller geometries and highly dense components designed into an IC device can adversely impact device reliability, manufacturing yields, cost, manufacturing times, and the like processes that are associated with an IC device. Additionally, some components (e.g., a processor) in an IC device may be created by use of a certain fabrication process (e.g., smaller node size) that may be incompatible with processes that may be used to create other components (e.g., a memory cell requiring larger spacing) or elements in the same IC device.
FIGS. 1A and 1B are three-dimensional diagrams of structures in an example IC device. FIG. 1A illustrates a Si substrate 101 and included structures 103 and Si fins 105 that may be constructed by use of a fin-type fabrication process. Details of an example section 107 are shown in FIG. 1B, which illustrates source/drain S/D (or D/S) regions 109 and 111, each including a S/D contact 113 (e.g., of Tungsten) and a silicon oxide-cap 115. Additionally illustrated is a metal gate 117 with a nitride-cap 119 and dielectric spacers 121 (e.g., carbon-doped silicon-oxide, SiOC), on opposite sides of each metal gate 117 and nitride-cap 119, that separate the metal gate 117 and its nitride-cap 119 from adjacent S/D regions 109 and 111 and their oxide-caps 115.
FIG. 1C illustrates a layout diagram including a gate contact and adjacent gate cut in an example IC device. The diagram includes metal gate structures 117 where at least one gate structure, 117a, is connected to a metal line 123 (e.g., above the gate) with a gate contact 125. Additionally, the metal gate structure 117a includes a gate-cut 127 that is in close proximity to the gate contact 125. The layout illustrated in FIG. 1C may be associated with a SRAM component that is to be implemented, along with other components and elements, in an IC device. As noted, with reduced/shrinking geometries used in design and fabrication of IC devices, it can be challenging to continue to reduce spacing 129 between the gate contact 125 and the gate cut 127 while meeting fabrication constraints for fabricating such a component.
A need therefore exists for a methodology to create reliable gate contacts in close proximity to gate cuts in an IC device and the resulting device.